1. Field of Invention
The present invention relates to a layout for enhancing driving ability of a signal path from a printed circuit board to an bonded integrated circuit. More particularly, the present invention relates to a layout of a signal path from a printed circuit board to a bonded integrated circuit, which by reducing capacitance of the layout to improve driving ability of the integrated circuit.
2. Description of Related Art
Chip-on-Glass (COG) product needs different power supplies for providing power sources to circuits integrated in the COG product. However, for scaling down a size of the integrated circuits (ICs), the scale-down layouts of the IC cause the width of power line structures being not wide enough to provide enough driving ability or being damaged. For example, FIG. 1 shows a layout of a COG product, which includes a power supply portion 110 and a circuit portion 120 bonding thereon. If some damages occurs in one of the line structures, as denoted as “112”, for example, and the damaged line structure is used for supplying power source to the circuit portion 120, it will cause the failure of the power supply.
In other case, if the width of the line structure is restricted and can not be wide enough for providing sufficient driving ability, it will also cause the power supplying failed. As shown in FIG. 1, if the line structures are used for providing a gamma driving reference voltage (GVDD), a gate driver power supply voltage (VGH), or a source driver power supply voltage (AVDD) and the like for a display, the driving ability of the line structures is an important issue for the display. If the width of the power line is too small, for example, 11 um, some yield loss will occur because of the shortage of driving ability of the power line.